1. Technical Field
The present invention relates to a semiconductor circuit, and more particularly, to a power source circuit and a semiconductor memory circuit using the same.
2. Related Art
FIG. 1 is a block diagram of a typical semiconductor memory circuit. Hereinafter, for the sake of convenience, a typical semiconductor memory circuit 10 having a 2-GB memory capacity will be explained as an example.
As illustrated in FIG. 1, the semiconductor memory circuit 10 is illustrated to have a total of 2-GB memory: a 1-GB memory is implemented by sixteen upper memory regions and a 1-GB memory is implemented by sixteen lower memory regions, when viewed from the center of the semiconductor memory circuit 10.
The semiconductor memory circuit 10 includes a plurality of memory regions (thirty-two memory regions) 64M_R and 64M_L, and four drivers 11 through 14 which generate a core voltage (VCORE) for defining data levels of memory cells included in the memory regions 64M_R and 64M_L.
The plurality of drivers (four drivers) 11 through 14 which generate the core voltage (VCORE) are provided in order to stably supply an amount of electric current necessary for the 2-GB memory.
The number of the drivers may be changed, depending on a circuit design or a memory capacity.
The plurality of drivers 11 through 14 consume electric current constantly for their operations right after the supply of the power to the semiconductor memory circuit.
The semiconductor memory circuit is manufactured on a wafer in a chip type, and whether a corresponding chip is usable is verified through various tests.
When any of the memory regions is failed due to process parameters or foreign particles, the failed memory region is replaced with redundancy cells.
As such, when all fails are replaceable with redundancy cells, the chip may be packaged as a 2-GB memory and shipped out.
Meanwhile, when many fails occur in a chip so that they may not be replaced with the redundancy cells, the corresponding chip is discarded.
However, in some cases, the fails in the upper 1-GB memory region of FIG. 1 may not be replaced with the redundancy cells while the fails in the lower 1-GB memory region may be replaced with the redundancy cells.
In those cases, the chip may be packaged as a 1-GB memory using only the lower 1-GB memory region and then shipped out.
In case of the 1-GB memory, a necessary electric current may be sufficiently supplied by only a small number of drivers, for example, two drivers.
However, even when the chip is packaged as the 1-GB memory, the four drivers 11 through 14 are included inside the chip, and the four drivers 11 through 14 consume electric current constantly for their operations right after the supply of the power to the semiconductor memory circuit.
Therefore, the typical semiconductor memory circuit may have a problem in that an amount electric current consumption is increased by the operation of unnecessary drivers, which is inappropriate for the memory capacity.